1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the use of tiling features to improve latch-up immunity of an integrated circuit.
2. Description of the Related Art
Latch-up is the condition where parasitic devices inherent in many CMOS structures cause the CMOS structure to enter an electrical state unrelated to its normal operation. This is often manifested as an abnormal high current conduction state which may be transient, may disappear when the triggering stimulus is removed, or may be permanent in the sense that the structure becomes frozen in that state as long as power continues to be applied. Unless the current in the latch-up state is somehow limited, it can also be destructive. Unfortunately, the problem of latch-up increases as CMOS device and circuit dimensions are scaled down, requiring a chip designer to make design tradeoffs to optimize the structure in order to avoid latch-up, typically by increasing the device and/or circuit area.
Accordingly, there is a need for improved CMOS structures and methods to provide improved latch-up immunity which overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.